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POLYTEDA Software Corporation will be presenting its latest technology at DATE09 - Design, Automation and Test in Europe trade show on April 20-24, 2009 in Nice, France. The company will introduce newest product PowerDRC. This is new generation physical verification tool designed specifically for high-efficient processing of extra-large layouts for deep sub-micron technologies – 45/32 nm and below. For more information please visit our booth B10 or click here to check DATE09 web site.
POLYTEDA Software Corporation received good response from Japanese semiconductor community during presentation of new physical verification technology on EDS Fair on January 21-22, 2009 in Yokohama, Japan. Representatives from major microelectronic companies visited POLYTEDA's booth. Local media shows interest to next generation DRC/LVS product - to see interview of Vlad Marchuk, President & CEO, published by E-Demo.net click here.
POLYTEDA Software Corporation will be presenting its next generation physical verification technology PowerDRC at DATE 09 - Design, Automation & Test in Europe conference on April 20-24, 2009 in Nice, France. The company will introduce newest product to European electronic design audience. PowerDRC is new generation physical verification tool designed specifically for high-efficient processing of extra-large layouts for deep sub-micron technologies – 45/32 nm and below. For more information please visit our booth #10 at the exhibition.
POLYTEDA Software Corporation will be presenting its latest technology at Electronic Design and Solution Fair on January 22-23, 2009 in Yokohama, Japan. The company will introduce newest product PowerDRC. This is new generation physical verification tool designed specifically for high-efficient processing of extra-large layouts for deep submicron technologies – 45/32 nm and below. For more information please visit our booth #110 or click here to check EDSFair web site.
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Modern and future 45/32 nm and below technologies are bringing new challenges for EDA tools. Physical verification is one of design flow areas where complexity of new processes in layouts combines with huge amount of data. On other hand, semiconductor industry still uses DRC/LVS tools that are based on core algorithms and principles created in last century. It creates significant bottleneck in design process causing losses of time and money for semiconductor companies.
To address requirement of modern and future designs, POLYTEDA Software Corporation is developing next generation physical verification system based on new revolutionary approaches. New tool is using unique proprietary set of algorithms and principles. Among them are processing subset of rules for several layers in “one shot”, parallel and distributed processing based on unique hierarchical approach, dynamic optimization of DRC/LVS process “on fly” using elements of artificial intelligence, and many others.
Usage of new technology allows reach speed close to theoretical limits. Preliminary calculation shows that new tool will be able to process the biggest currently available designs under one hour time limit. Almost linear speed dependency and scalability in handling huge amount of data allows processing layouts 10-100 times bigger than the biggest designs currently available.
PowerDRC will cover all physical verification needs of semiconductor industry at least for next 10-20 years. It is a tool that is going to last practically forever.
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Toronto, ON, Canada – POLYTEDA Software Corporation announced first evaluation results from beta-customer IHP GmbH (Germany).
Evaluation was done on variety of real designs based on BiCMOS technology. The designs include combination of logic and memory blocks. IHP GmbH tested performance, functionality and accuracy of PowerDRC. The tool was benchmarked against physical verification tool from world’s leading EDA vendor. Accuracy of the result was checked by XOR function performed on design rule violation markers in the layouts.
According to results, PowerDRC processing speed outperformed competitor tool by several times. The functionality provided by PowerDRC allowed running full rule deck, covering all required design checks.
Accuracy of results surpassed competitive tool: PowerDRC was able to detect real errors in the designs that were overlooked by tool from other EDA vendor...
For full text in PDF format click here.
Toronto, ON, Canada – Based on results of initial evaluation of new IC layout processing technology, POLYTEDA Software Corporation announced start developing of next generation physical verification (DRC/LVS) tool. The tool is target modern and future super large designs for 45-nm and below. In January 2008 the company secured round A financing for the project. Preliminary plans target beta-release in the end of 2008 – beginning of 2009.
The core element of layout processing technology was implemented in PowerLPU tool earlier in June 2007. During second half of 2007 various benchmarking and testing of PowerLPU proved the technology is the fastest in the world...
For full text in PDF format click here.
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