PowerDRC/LVS

POLYTEDA's core product, PowerDRC/LVS, is a tool for the physical verification of microelectronic circuits. It enables rapid verification of new designs to ensure accuracy, prior to mask creation and manufacturing.

PowerDRC/LVS is unique. It can process multiple design rules and design layers simultaneously.

PowerDRC/LVS dramatically reduces design cycle time, design iterations, compute infrastructure requirements and precious engineering time. Customers will benefit from reduced costs and enhanced opportunities to meet aggressive go-to-market windows.

In addition to superiority in processing speed, PowerDRC/LVS can handle huge amounts of data -- up to tens of billions of transistors. It's also compatible with design-rule syntaxes from leading competitors, allowing customers to port existing design infrastructures to PowerDRC/LVS for more efficient processing.

LVS debug can be very frustrating and can throw a design schedule out by weeks. Current debug environments available on the EDA market force the user out of the design cockpit to a secondary GUI, into a painful, laborious process of identifying errors and shorts.

PowerDRC/LVS was designed to eliminate these problems.

It is fast, accurate, and utilizes your current design environment to present errors in a rational way. Our DRC and LVS engines combined, provide a complete suite of error-browsing capabilities which overlays to your physical design environment or layout editor. Errors can be organized and categorized.