Advanced physical verification solutions
POLYTEDA Makes John Cooley’s “My Cheesy Must-See for DAC 2009” PDF Print E-mail
Wednesday, 01 July 2009 00:00

POLYTEDA Makes John Cooley’s “My Cheesy Must-See for DAC 2009”

You might want to print out a hardcopy of this to use as an unofficial guide to the San Francisco DAC exhibit floor next week.

  1.) If you want to see the "big news" that's at this year's DAC, it's
these C synthesis tools in the following order.

Mentor CatapultC -- C++, low power and control opto, used by ST,
Ericsson, Toshiba, Qualcomm, Hitachi, Panasonic, Fuji Xerox, Siemens,
Minolta, Thales, Pioneer, Telegent, Fujitsu, and Sanyo. Gary Smith
says CatapultC had #1 market share in 2008. (booth 3567) Ask for
Bryan Bowyer or Thomas Bollaert. Freebie: beer and wine.

Forte Cynthesizer -- SystemC, area-power-speed opto, used by Toshiba,
Sony, Samsung, Ricoh, Sanyo, Fujitsu, OKI, and Epson. Brett Cline
says Cynthesizer had #1 market share in 2008. (booth 1225) Ask for
Brett Cline or Mark Marshall. Freebie: caricatures, straps, pens.

Synfora PICO -- ANSI C, parallelism opto, used by Texas Instruments,
Olympus, and ST-Ericsson. Simon Napper says his power opto kicks
ass with 50% reductions. (booth 1440) Ask for Vinod Kathail.

AutoESL AutoPilot -- ANSI C/C++/SystemC, area-power-speed opto, used
by Microsoft, Raytheon, Xilinx. "We're layout aware!" (booth 3755)
Ask for Atul Sharan. Freebie: toy copter, sticky wall crawler

Why only C synthesis and why these four vendors? See gad071409.html

2.) At this DAC, Synopsys announces gate-level IR-drop and EM analysis
will be inside IC Compiler using embedded PrimeRail technology and
that "IC Compiler users don't need a standalone rail analysis tool
anymore!" -- which is bad news for the Apache Redhawk, Cadence
VoltageStorm, Magma Quartz Rail, and Sequence Cool products. Renesas
will share their results at the IC Compiler luncheon on DAC Monday.
(booth 1120) Ask for Li-Pen Yuan or Tom Chau. No freebie.

Apache RedHawk-NX supports hierarchical dynamic IR-drop and EM
analysis. In whitebox mode it has same accuracy as flattened analysis
with 30 to 50% performance improvements depending on the design.
Whereas graybox will result in 3 to 5% accuracy loss but will
provide 2x to 3x in performance. It uses pattern recognition for 2x
to 3x better memory use. It also does S-parameter package models.
(booth 722) Ask for Aveek Sarkar. Freebie: polar bear

3.) For min power tools, Sequence PowerArtist-XP lets "RTL designers,
without becoming power experts, can analyze, visualize and reduce
power by 10-60% within minutes on multi-million instances."
(booth 3455) Ask for Will Ruby. Freebie: hippie pens

Atrenta SpyGlass-Power does power estimation at RTL/gates, power
reduction by new clock gating at RTL, and supports CPF and UPF.
(booth 1528) Ask for Kiran Vittal. Freebie: card trick & t shirt

Calypto PowerPro CG automatically reduces power in registers,
clock trees, and combinational logic in RTL designs. AMD uses
it. (booth 1610) Ask for Venkat Krishnaswamy. Freebie: none

Incentia ECOCraft-Power gets, as an ECO, an "average of 20 percent
leakage power reduction on designs already optimized in P&R."
(booth 808) Ask for James Chuang or Steve Lin. Freebie: cards

4.) If you can qualify for Mentor's NDA agreement, see "Project Janus"
in the Mentor booth. The DFM/DRC heavy parts of Calibre are being
morphed into the Sierra Olympus-SoC router. On the non-NDA side,
Olympus-SoC P&R now does low power and floorplanning for 100+ million
gate chips. Apparently ST, Fujitsu, NEC, and AMD all now use Olympus.
(booth 3567) Ask for Sudhakar Jilla. Freebie: beer & wine

Magma Talus Vortex this year does "CCS-optimization, multithreading,
MCMM, CPF and UPF support, a RTL-to-GDSII reference flow manager
and Visual Volcano for graphical feedback on key design metrics."
(booth 1414) Ask for Rob Knoth. Freebie: pens

AtopTech Aprisa claims it's "up to 5X faster than the competition,
10 to 15% better timing, built for variabilty, makes DFM/DRC clean
designs, lower leakage power, fewer buffers added, easy to use."
It's everything plus the kitchen sink! Broadcom, Sharp, and Raza
use it. (booth 3167) Ask for Eric Thune. Freebie: beach ball

For Synopsys, the IC Compiler people are yarping about IC Validator
running inside ICC; PrimeRail running inside ICC; and that ICC now
"runs 2.5X faster MCMM with enhanced features". (What "enhanced"
means here, I don't know. (booth 1120) Ask for Mark Bollar.

Incentia ECOCraft-Timing does post-layout hold-time and setup-time
fixing ECOs. Claims MCMM, less buffers, CPF and UPF, and 2X-10X
faster. (booth 808) Ask for James Chuang. Freebie: playing cards

TSMC ISO Flow is a multi-tool RTL-to-GDSII IC implementation flow
with sign-off recommendations and scripts. It is "executable" and
process-specific, not a reference flow. All EDA tools used in the
flow are pre-qualified. TSMC 65nm std cell libs are included.
(booth 822) Ask for David Lan or Louis Liu. Freebie: blanket

5.) As Virtuoso killer #1, this year I recommend that you take a look
at Springsoft Laker because it's one of the older, more established
rivals to Virtuoso. Hell, it's one of only three PDK's that TSMC
natively supports! Users are Marvell, TSMC, MediaTek, Samsung,
Hynix. This year Laker's added Pyxis integration for DFM-aware
routing. (booth 3367) Ask for Roger Kang. Freebie: 2 GB flash

As Virtuoso killer #2, Magma Titan ADX handles layout effects 40 nm
and below during optimization. It's simulation is driven directly
from optimization. It's parallel solver and dynamic modeling helps
device model accuracy. Library models range from nifty ADCs to
high-speed SERDES. Users are Panasonic, TSMC, Rambus. (booth 1414)
Ask for Mar Hershenson or Ashutosh Mauskar. Freebie: pens

As Virtuoso killer #3, [new at DAC] Orora Arsyn. Custom design and
reuse of xistor IC's. Arsyn takes a parametric netlist with various
circuit topology, device type and size options as input, and outputs
designs meeting the specs for a given process. Users Boeing, Sanyo.
(booth 4151) Ask for Lili Zhou. Freebie: Starbucks gift cards

As Virtuoso killer #4, Synopsys Custom Designer added simulation and
what-if analysis for IR drop results. Bad news for Apache Redhawk.
(booth 1120) Ask for Geoff Ying or Neal Gopalan. Freebie: t shirt

As Virtuoso killer #5, old school Tanner EDA has added it new L-Edit
SDL Router
to this field. It's an interactive autorouter for analog
cells and top-level chip assembly and it allows designers to manually
route nets, or parts of nets, and let the auto-router do the rest.
Philips uses it. (booth 3655) Ask for Jeff Miller. Freebie: cards

As Virtuoso killer #6, Analog Rails new features since DAC 2008:
auto sizing of devices with global and local optimizer, auto analog
placer, auto differential routing with shields, auto digital std
cell generator, auto digital placer, enhanced auto off-grid/on-grid
router, and 3D parasitic extraction of devices & routes. "No VC's.
Just 27 developers, mostly in Arizona, who are our shareholders."
(booth 3542) Ask for Cliff Wiener. Freebie: Same surly attitude

For Virtuoso killer PDKs, try IPL. OA-based and open, unlike CBDA,
SKILL, etc. This year TSMC has 65nm iPDKs plus and the roadmap for
40nm and 28nm TSMC iPDKs. (booth 1016) Ask for Jingwen Yuan.

To get by Cadence SKILL PCells, Check out Ciranova PyCell Studio.
(booth 4400) Ask for Dave Millman. Freebie: LED flashlights

6.) For Virtuoso add-ons, Skillcad StepRouter is seamlessly integrated
into Cadence Virtuoso (both IC5 and IC6), and offers extra automation
for path/bus routing and matched path/bus routing in custom layout.
Connections are "optimized, by Layer-Direction Cost, R, C or RC,
along user-guided routing-coordinates" plus it "increases custom
layout wiring speed by 20x". (booth 3261) Ask for Pengwei Qian.

Solido Variation Designer runs in a Virtuoso environment to solve
for process variation problems (statistical, proximity) in AMS
circuits to balance yield vs. power & area requirements. Now they
can "solve for well proximity effects at the circuit design stage".
(booth 3060) Ask for Kris Breen or Amit Nanda. No freebie.

[New to DAC] Micrologic nanoRVInteractive performs reliability
checks such as electromigration, antenna and fuse effects, IR Drop,
etc. interactively as the layout is being done. It makes higher
quality designs due because it catches problems before simulation.
(booth 3259) Ask for Danny Rittman. Freebie: none

Sagantec Anaconda-M does automatic process migration of AMS and
custom IP to a new technology node or a different foundry. It runs
in Virtuoso and accelerates the time to tape out by more than 2x.
(booth 1307) Ask for Dan Blakely. Freebie: t-shirt

7.) If you're tired of Design Compiler, you should check out the new
Oasys RealTime Designer. It takes the RTL for an entire chip
along with the floorplan (it will create a seed floorplan if you
don't have one) and synthesizes a placed netlist within the context
of that floorplan. They claim it's 10 - 60X faster than Design
Compiler and can handle 100 M gate designs. Renesas uses them.
(booth 3061) Ask for Sanjiv Kaul. Freebie: t-shirts

New at DAC, Synopsys has added "DesignWare minPower components" to
its Design Compiler library. It optimizes the datapath based on
power costing and switching activities and gets up to 21% power
reduction. (booth 1120) Ask for Jay Chiang. Freebie: none

8.) For those who think PrimeTime is past its prime, Extreme DA GoldTime
does "nominal and Statistical Static Timing Analysis including SI
and its really FAST!" plus it "uses Parametric OCV; no library re-
characterization needed." Customers are Nvidia, PMC-Sierra, STARC.
(booth 1710) Ask for Guy Maor. Freebie: multi-color highlighters

CLK-DA Amber FX either replaces or complements PrimeTime by doing
a fast SPICE run on every critical path you select in your design
plus Monte Carlo analysis. It's SSTA. Amber FX is part of the new
TSMC 10.0 Reference Flow. (booth 3951) Ask for Isadore Katz.

Incentia TimeCraft also does "STA, SI, SSTA, and Power Analysis"
plus claims "2X to 5X speedup" MCMM on 50 M gate, 40 nm tapeouts,
CPF and UPF, cross-talk pessimism reduction, and location-based OCV.
(booth 808) Ask for James Chuang or Steve Lin. Freebie: cards

9.) Mentor Calibre nmDRC Waiver Flow automates the tracking of DRC
waivers during full-chip verification of SoCs incorporating IP from
multiple sources. It minimizes missing real errors w/o increasing
reporting of false errors. (booth 3567) Ask for Michael White.

Mentor Calibre PERC lets you automate unique, customer-specified
electrical rule checks (ERCs), like ESD checks, using both netlist-
and layout-based rules. (booth 3567) Ask for Carey Robertson

Magma Quartz DRC/LVS are "3X-10X faster and NOW offers Direct Read
of Calibre runsets, making Quartz the must see for DRC/LVS."
Customers include TSMC, IBM, Nvidia, Toshiba, Samsung and Chartered.
(booth 1414) Ask for John Lee. Freebie: pens

For DRC/LVS, Synopsys is "de-emphasizing" Hercules to force users to
their new IC Validator DRC/LVS. Upside: ICV works fast *inside* ICC.
Downside: confusion whether ICV works *outside* of ICC. Toshiba and
Nvidia use it. (booth 1120) Ask for Rahul Kapoor. Freebie: none

[New to DAC] Micrologic VisualDRC imports the signoff DRC rules into
Virtuoso or Laker checking the rules on-the-fly with visual feedback,
enabling correct-by-construction layout. "Shortens layout by 40-50%."
(booth 3259) Ask for Danny Rittman. Freebie: none

[New to DAC] PolyTEDA PowerDRC is an edge-based Design Rule Checker
"for those looking for a good alternative to Calibre or Hercules."
(booth 814) Ask for Mike Zatezalo. Freebie: flashlight screwdriver

10.) In so-called "Intelligent Testbenches", Springsoft's Certitude
(which they got when they acquired Certess last year) injects bugs
into your design to see if your current testbench catches them.
Intel, ST, SanDisk, Ericsson, Broadcom uses them. (booth 3367)
Ask for Jean-Marc Forey. Freebie: 2 GB flash drive

Nusym Denibulator does the same thing but also "analysis to directly
build insight into the specified coverage points and provide the
test vectors needed to hit them". Qualcomm uses Nusym. (booth 622)
Ask for Alex Sibelescu. Freebie: protein bars

11.) For clock-domain-crossing bugs, Real Intent pimps Meridian CDC.
It handles free-running clocks, hierarchy, and messy FIFOs.
(booth 1728) Ask for Prakash Narain. Freebie: back packs

Jasper JasperCore allows users to cheaply implement multiple proofs
and applications, across multiple cores and computers, "efficiently
serving multiple users, even across multiple business units."
(booth 3767) Ask for Rajeev Ranjan. Freebie: 1 GB flash drives

OneSpin 360 MV is a "family of tools for formal assertion-based
verification from early automatic RTL analysis and block-level
verification all the way to System Verilog Assertions (SVA)."
(booth 3465) Ask for Michael Siegel. Freebie: puzzle

12.) EVE ZeBu-Server is a scalable emulation system, expandable to one-
billion ASIC-equivalent gates. That's 1,000,000,0000. Use multi-
user, multi-mode at 10 MHz on a 10-million gate design. Compile
1 B gates at a rate of 100 M ASIC gates per hour on a PC farm.
Users are Apple, AMD, Broadcom, Fujitsu, Intel, LSI, Marvell, NEC,
Northrop Grumman, NXP, Qualcomm, Renesas, Sanyo, ST, TI, Toshiba.
(booth 908) Ask for Lauro Rizzatti. Freebie: money-clips

Synopsys Synplicity HAPS is an Altera Stratix-III FPGA prototyping
board "for high performance simulation and validation. After
validation, the same model can be used with the Synplify DSP tool
to explore architectural optimizations and automate handoff to ASIC."
(booth 1120) Ask for Doug Johnson or Chris Eddington. No freebie.

The Dini Group has a new Altera Stratix-IV protoboard, and they're
starting to ship Xilinx Virtex-6. (booth 1878) Ask for Mike Dini.

13.) For analog mixed-signal tools, Pulsic Unity does "placement, routing,
hierarchical floorplanning, editing, SI, ECO and timing analysis for
mixed A/D, anything non-ASIC! Reads/Writes CDBA/DFII, LEF/DEF, OA,
Spice, CDL, SDC, Verilog, .lib etc.; you name it we do it." Used by
SanDisk, Altera, Samsung, Hynix, Toshiba, Oki, NEC, Sony, Micron.
(booth 815) Ask for Mark Waller or Steve Ferguson. Freebie: pen

Ciranova Helix does AMS floorplanning and placement, concurrent trial
routing for parasitics, TSMC iPDK, used on designs over 40 K xistors.
(booth 4400) Ask for Dave Millman. Freebie: LED flashlights

Apache Totem is a layout-driven full-chip transistor-level power
integrity and substrate noise analysis tool. "It expands our power
and noise product offering from SoC digital to AMS designs."
(booth 722) Ask for Aveek Sarkar. Freebie: stuffed polar bear

[New to DAC] Mephisto M-Design does AMS IP creation, verification,
documentation and migration at different abstraction levels.
(booth 521) Ask for Kenneth Francken. Freebie: clocks

14.) Tanner EDA HiPer PX extracts interconnect parasitics and produces an
RC finite element model for simulation. Extraction can be performed
using 2D table interpolation or a boundary element 3D field solver.
(booth 3655) Ask for Jeff Miller. Freebie: travel playing cards

Magwel Power Transistor Modeler extracts resistance and displays
hot-spots in large power transistor arrays with 3D accuracy.
(booth 3357) Ask for Mike Stuber or Dundar Dumlugol. No freebie.

[New to DAC] Silicon Frontline F3D and R3D does parasitic extraction
with lots of vague claims. (booth 3165) Ask for Yuri Feinberg.

15.) For "constrant" tools, FishTail Focus now merges multi-mode SDC
files into a single super mode constraint file -- which cuts STA
and P&R runtime drastically. TI is presenting on this tool.
Like Atrenta below, FishTail ReFocus also does EC on constraints
now, too. (booth 3064) Ask for Ajay Daga. Freebie: nothing

In this same space, Real Intent PureTime also sniffs your SDC/Tcl
constraints for set_false_path and set_multicycle_path issues.
(booth 1728) Ask for Prakash Narain. Freebie: wine glasses

Atrenta SpyGlass-Constraints does equivalence checking this year
for constraints and designs at various stages like RTL, netlist,
pre-layout, post-layout. Renesas, ST, Samsung use this tool.
(booth 1528) Ask for Ron Craig. Freebie: card trick and t-shirts

16.) This year in floorplaning, Magma Hydra now supports "channel style,
near abutment, and full abutment" plus "automated partitioning,
shaping, macro placement, and pin assignment". A bunch of companies
use Hydra: ClearSpeed, Renesas, Texas Instruments, eSilicon, Uniquify,
ARM, Open-Silicon, STARC, Toshiba. (booth 1414) Ask for Rob Knoth.

I've heard the Mentor Sierra folks are working on "Project Tetris"
to add 100+ M gate capacity floorplanning, chip assembly, and chip
finishing to Olympus-SoC. (booth 3567) Ask for Sudhakar Jilla.

Atoptech Apogee does "topdown chip planning, partitioning, bottom-up
chip assembly and chip-level timing closure" and it "Loads the full
hierarchical netlist and parasitics in minutes". Claims 3 tape-outs.
(booth 3167) Ask for Daniel Maung. Freebie: beach ball

Duolog Socrates Weaver does automated SoC/IP integration using IP
packaging and assembly rules. (booth 2028) Ask for David Murray.

17.) [New to DAC] Entasys Pillar DP seems to live between estimating a
chip design and actually doing a design's floorplanning. It does
"power and area estimation, block level floorplan, power network
prototyping and I/O pads configuration" and also "chip/package co-
design flow with BGA editor and chip-to-package connectivity editor"
plus "allows front-end designers to review post-layout design with
STA report in ECO design stage". Samsung did 45 nm with Pillar DP.
(booth 3863) Ask for SungHwan Oh or JeongHwan Yoon. Freebie: pen

Cadence's has added SoC Encounter so it can give
more realistic estimates. (booth 1100) Ask for Adam Traidman.

18.) Axiom MPSim is a full multi-CPU simulator for System Verilog,
OpenVera and SystemC. It provides full support for 64-bits, SDF,
VPI, SVA, code coverage, FSM Coverage, functional coverage and test
grading. Cortina, Ikanos, Matisse, Microsoft, Exegy are customers.
(booth 1815) Ask for Tarak Parikh. Freebie: backpacks

SpringSoft Siloti & Verdi debug VCS/ModelSim/NC-Sim Verilog runs.
It has "integrated waveforms, source code, schematics for testbench,
RTL, and gate levels, with unique automated tracing capability that
unrolls logic over time". Think of it as deBussy II. Intel, ST,
AMD, Sun, Broadcom, Qualcomm, NEC, nVidia, Marvell all use it.
(booth 3367) Ask for Bindesh Patel. Freebie: 2 GB flash drive

Synopsys VCS has added multi-core support that "can speed up your
long running Verilog simulations by 2X". Supports NTB and System
Verilog. (booth 1120) Ask for Albert Chiang. Freebie: t-shirt

In the linter-on-steroids dept, look at Real Intent Ascent. It
catches errors such as dead code, state machine deadlocks, path-
based and x propagation stuff. Users NEC and AMD. (booth 1728)
Ask for Prakash Narain. Freebie: wine glasses and back packs.

19.) For fruity C tools, ChipVision PowerOpt analyzes a C/C++/SystemC
design for power consumption and then synthesizes the lowest-power
architecture to Verilog RTL with a testbench and constraints.
(booth 3555) Ask for Paul Chaffey. Freebie: 1 GB flash drives

Calypto SLEC does equivalence checking between your C/C++/SystemC
system-level model and any RTL generated by whatever. It can also
verify that two system-level models are functionally equivalent.
(booth 1610) Ask for Gagan Hasteer. Freebie: none

Target Compiler lets you use their proprietary nML language to
create custom processors. Then they synth it to RTL. Thrown in
is a C compiler that lets you run programs on your custom processor.
Atmel, Freescale, Gennum, Nokia, NXP, Sanyo, Sensata, ST, TI uses
them. (booth 3365) Ask for John Fox. Freebie: Post-it notes

20.) For architectural tools, Bluespec is for using high-level models,
transactors, testbenches, and legacy IP for SoCs. It's the only
arch tool that synthesizes to FPGAs. Qualcomm, IBM and Intel uses
it. (booth 3851) Ask for George Harper. Freebie: tins of mints

[New to DAC] Mirabilis VisualSim is a system-level lib of 400 pre-
built components that let's you decide the HW/SW partition of your
SoC plus does power/speed estimates on it. It's for architects.
(booth 3345) Ask for Deepak Shankar. Freebie: toothbrush

Carbon Model Studio compiles RTL into high speed software objects
which link into virtual platforms. Carbon SoC Designer is their
cycle-accurate virtual platform. They claim "50+ customers".
(booth 3359) Ask for Bill Neifert or Matt Grasse. No freebie.

Atrenta 1Team-Genesis also plays in this niche with "architectural
feasibility analysis to enable early power and physical planning".
This year they've added "IO pin-mux gen and Register Management"
(booth 1528) Ask for Sameer Patel. Freebie: card trick & t shirt

Agnisys IDesignSpec also does "Register Management" for IP and SoC.
(booth 4064) Ask for Anupam Bakshi. Freebie: laser pen

21.) Berkeley Analog FastSPICE "produces identical results to Spectre and
HSPICE (guaranteed) 5x-20x faster on circuits of 10 million elements,
and has the only true SPICE accurate device noise analysis." Users
are Broadcom, Fujitsu, NXP, Samsung, Toshiba, TI, LG, and Atheros.
(booth 1620) Ask for Scott Guyton or Matthew Parker. Freebie: pens

Nangate MegaLibrary is a digital library with 10,000 cells rich in
logic functions, topologies, drive strengths which Design Optimizer
feeds to Cadence, Magma, Synopsys and Mentor synthesis/PNR tools.
This cherry picked std cell lib gives your design killer performance.
(booth 3265) Ask for Jens -- there's 6 Jens there! Freebie: clocks

Prolific ProDFMOptimizer is a "DFM tool that's a bit different: it
optimizes only cell-level GDSII, where it's aware of performance,
power, and yield issues. It won't reduce the area of a cell, but
it can improve a cell's routability significantly." (booth 3543)
Ask for Paul de Dood. Freebie: t-shirt

Z Circuit ZChar lib characterization for mem, std cell, & IO pad.
(booth 1010) Ask for Fred Obermeier. Freebie: chocolates

Magwel Substrate Noise Modeler simulates substrate noise injection
and coupling in power transistor & RF ICs. It models both minority
and majority carrier noise injection; models drift-diffusion in the
substrate "while others have a resistive model only." (booth 3357)
Ask for Mike Stuber or Dundar Dumlugol. No freebie.

22.) Some unexpected memory stuff at DAC this year. Denali Databahn
Memory Controller
lets your chip use low-cost, high-speed external
DRAM (including DDR2, DDR3, LPDDR1, LPDDR2). Denali Databahn NAND
Flash Controller
is for "all raw NAND Flash devices (including ONFi
1, 2 & Toggle devices)" plus it gives "a PHY for async as well as
high-speed NANDs". (booth 1424) Ask for Marc Greenberg.

LogicVision ETMemory does memory BIST and self-repair. It's a "new
power-aware version. On-chip engine keeps track of voltage island
power activities and ensures that any re-activated defective memory
is properly reconfigured." Broadcom, Sandisk, and Intel uses them.
(booth 1614) Ask for Steve Pateras. Freebie: foldable frisbee

Calypto PowerPro MG is the "only tool to automatically modify RTL
to reduce dynamic and leakage power in embedded SoC memories."
(booth 1610) Ask for Venkat Krishnaswamy or Sumit Roy.

Interra MC2 lets designers define reusable architecture for standard
or embedded memories" plus it "can define placement, netlist, timing,
frontend/backend models, datasheet format, BIST/BISR needs, and
characterization points for your memory architecture. Cypress, Sun,
and On Semi use MC2. (booth 1316) Ask for Vijeta Kashyap.

Denali PureSpec this year added PCIe 3.0 and USB 3.0 support,
integrated test plan support, and a powerful capability for
protocol-aware exploration and "intuitive debugging." (booth 1424)
Ask for Josh Filliater. Freebie: Denali party tickets

23.) For Design Data Management, ClioSoft is showing its SOS tool used by
Marvell, SUN, AMCC, Analog Devices, & IDT. It now supports Synopsys
Custom Designer this year plus Cadence Virtuoso, Mentor ICstudio and
SpringSoft Laker data. (booth 3651) Ask for Michael Henrie.

IC Manage also added support for Synopsys Custom Designer "including
library manager integration with version and icon annotation, atomic
checkins as well as custom widgets for sync, checkouts and revision
history". Users Kodak, AMD, Nvidia, Rambus plus I heard IC Manage
stole Cypress and Maxim from Dassault/Synchronicity DesignSync.
(booth 1810) Ask for Shiv Sikand or Dennis Harmon. Freebie: candy

[New to DAC] Methodics VersIC does DDM on the Subversion, Perforce,
or ClearCase platforms. Used by Cirrus Logic, Netlogic Microsystems,
Bosch, Tabula. (booth 1924) Ask for Simon Butler. Freebie: t-shirt

In a weird subcategory, TeamEDA sells LAM, "Licence Asset Manager",
which tracks EDA license assets (shared and node-locked), including
Vendor info, Tool info, PO's, Costs, License info, Servers, daemons,
current check-outs, historical usage patterns and trends. Vitesse,
AMCC, Northrop Grumman uses it. (booth 910) Ask for Guy Haas.

24.) For package guys, Apache Sentinel "does package/PCB PI, SI, thermal,
and EMI analyses. Sentinel-PI extracts true 3D full-wave broadband
models of package and board power nets. Sentinel-TI is a IC-package
thermal co-analysis tool. Sentinel-EMI does EMI. Sentinel-SSO checks
for SSO". (booth 722) Ask for Aveek Sarkar. Freebie: polar bear

[New to DAC] E-System Sphinx is a signal & power integrity co-
simulator for IC Package & PCB design and "If your IC package and
PCB designs have any split planes, voltage islands, cavities, gaps,
or any other apertures, and you want to avoid costly re-spins, you
need to come by and talk to us before you tape out your next design."
(booth 508) Ask for Gene Jakubowski. Frebie: t shirts and pens

[New to DAC] Docea ACEplorer does modeling and simulation of low
power/thermal architectures for early analysis of risks that threaten
reliability such as IR-Drop or thermal runaway. (booth 3143)
Ask for Ghislain Kaiser. Freebie: baptismal water

25.) Verific sells System Verilog and VHDL frontend parsers in C++ for
EDA vendors. Synopsys, Magma, Denali, EVE, Sequence, Springsoft uses
them. Check out their new static timing analysis component. It is
ready and they're actively looking for beta customers. (booth 3545)
Ask for Rob Dekker or Michiel Ligthart. Freebie: stuffed giraffe

Imera sells remote-debug-over-the-Internet tools to EDA vendors like
Cadence and Synopsys so they can instantly remote debug user problems
without requiring designers to transfer their IP away from home.
(booth 3964) Ask for Tim Goh or Alex Jen. Freebie: pens

26.) You may have noticed that no Cadence tools were listed in my Cheesy
Must See List here. That's because Craig Johnson, VP of Corporate
Marketing at Cadence
forbid any CDNS employee from nominating his/her
tools for this DAC best-of-class competition. Why? "Our approach
is to build complete solutions that take advantage of our point
technologies," Craig emailed me. Craig added he emailed his Cadence
flows to "tens of thousands of customers". So from how I understand
it, CDNS' strategy at this DAC is not to compete for best-in-class,
but instead to try to sell all-Cadence flows to the existing Cadence
customer base. Locking in the users brings max dollars for CDNS.
"Who's this monopoly-thinking Johnson guy?," I wondered. On his bio
I found that he was an '04 Intel Mike Fister appointee. Enough said.
(booth 1100) Ask for Craig Johnson. Freebie: your co's checkbook

Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)

John Cooley
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