Advanced physical verification solutions
PowerDRC/LVS 1.7.1 released PDF Print E-mail

Kiev, Ukraine, March 19, 2014 - POLYTEDA UKRAINE LLC, a provider of semiconductor design software, today announced the general availability of PowerDRC/LVS version 1.7.1.

This release is dedicated to delivering new functionality:

  • Support of $fill operation was added in PowerDRC allowing to create an array of rectangles of specified dimensions and spacing for use in dummy fill creation
  • ParDRC work in the hierarchical mode was improved
  • PowerRDE got four controls for Hierarchical mode and two more controls for explicit listing of flat and hierarchical cells in Extraction mode

Please review Release Notes for more information. 

PowerDRC/LVS is designed to process integrated circuit (IC) designs of  various size at technology nodes up to 40nm, with run times which are fast and completely predictable. It is massively scalable and provides turnaround time that is up to an order of magnitude faster than existing solutions. PowerDRC/LVS achieves this scalability and turnaround time through the use of a unique data structure and innovative window scanning technique. 

Foundry Support

During beta test period, POLYTEDA worked with wilde list of partners and evaluators to validate accuracy and performance for production. Contact us to learn more about the availability of foundry rule decks.

Availability and Demonstration

PowerDRC/LVS 1.7.1  is available now from POLYTEDA. Contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for more details.


POLYTEDA UKRAINE LLC is a rapidly growing design automation company, focused on providing fast, accurate and affordable verification solutions for electronic design companies. For more information about POLYTEDA and its products, please visit